Quantum Experimental Pilot Lines for Quantum Technologies

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Expected Outcome: This action will strengthen Europe's leadership and strategic autonomy in quantum technologies by advancing experimental pilot line capacities as a vital stepping stone toward future industrial-scale quantum hardware production. Qu-Pilot serves as the critical intermediary between academic research and the stable pilot lines under the Chips Joint Undertaking, offering a testbed for technological innovation, reproducibility, and manufacturability. Expected outcomes include: Deployment of experimental quantum pilot lines addressing diverse platforms and materials, laying the groundwork for broader integration into Chips JU pilot lines. Establishment of scalable and reproducible quantum fabrication processes, advancing TRL 4–6 technologies and addressing early-stage certification, standardisation, and quality control. Reinforcement of a pan-European quantum hardware ecosystem through shared infrastructure and open-access models, fostering participation from SMEs, startups, and research institutes. Demonstrated ability to accelerate technology maturity and feed critical feedback loops into future Chips JU stability pilot lines. Enhanced synergies with testing infrastructures (e.g., Qu-Test), standardisation efforts, and industrialisation roadmaps, enabling horizontal integration across computing, communication, sensing, and enabling tech domains. Scope: The action is to implement the pilot production elements of the Qu-Pilot Framework Partnership Agreement. The proposal should advance the maturity of quantum hardware technologies in alignment with EU industrial strategy, emphasising flexibility, innovation, and scalability. The proposal should address: Establishment or enhancement of experimental pilot production infrastructure for TRL 4–6 quantum hardware technologies, with strong R&D orientation. Development of pre-industrial processes for: Quantum processors (e.g., superconducting, trapped ions, photonic), Quantum sensors (e.g., NV centers), Cryo-compatible packaging and interconnects. Integration of cleanroom capabilities with lithography, etching, and deposition tailored to quantum device requirements (e.g., silicon, diamond, III-Vs), ensuring convergence with Chips JU standards. Creation of collaborative fabrication access models (shared-cost basis) open to academic and industrial partners. Development of standardised workflows for yield analysis, reproducibility, and quality assurance, supporting component certification pathways. Continuous engagement with Qu-Test and other testbeds to enable rapid iteration cycles and technology validation. Active alignment with Chips JU’s pilot line roadmap to enable seamless transfer of validated technologies once the stability pilot lines are operational. Contribution to a transversal European infrastructure serving multiple quantum domains (computing, sensing, communications), ensuring cross-domain integration and maximising synergies. Technology Readiness Level - Technology readiness level expected from completed projects The rules are described in General Annex B of the Horizon Europe Work Programme 2026-2027. Activities are expected to validate technologies starting at TRL 3/4 and confirm their progression to TRL 5/7 by the end of the project.

Reproduced verbatim from the official notice — only the wording is the source's; we split it into sections for readability.

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